1. Field of the Invention
The present invention relates to a semiconductor device comprising a plurality of memory cores implemented on a semiconductor chip, and a system in which the semiconductor chip and a control chip are stacked.
2. Description of Related Art
In recent years, a system has been proposed in which a multi-core memory including a plurality of memory cores is configured and a three-dimensional stacked structure is formed using through electrodes (TSVs: Through Silicon Vias) (for example, see Non-Patent Reference 1). Assuming a multi-core DRAM chip in which such a structure is applied to DRAM (Dynamic Random Access Memory), each DRAM core included in the multi-core DRAM chip is required to perform high-speed data communication through the TSVs. In order to achieve a high-speed multi-core DRAM, it is important that circuits including a data bus and an I/O circuit that transmit data through DQ terminals operate in high throughput. Further, the high-speed operation of these circuits requires measures against an increase in consumption current, influence of power supply noise between the circuits, and the like. Particularly, since various power supplies are used in accordance with functional blocks in a general configuration of DRAM (for example, see Patent Reference 1), it is desirable to suppress an increase in consumption current and cross-coupling noise between the circuits not only in a memory region, but also in peripheral circuits including the data bus, the I/O circuit and the like.    [Patent Reference 1] Japanese Patent Application Laid-open No. 2003-7059 (U.S. Pat. No. 6,411,560) [Non-Patent Reference 1] K. Ono, A. Kotabe, Y. Yanagawa and T. Sekiguchi, “1-Tbyte/s 1-Gbit DRAM Architecture with Micro-pipelined 16-DRAM Cores, 8-ns Cycle Array and 16-Gbit/s 3D Interconnect for High Throughput Computing,” IEEE Symposium on VLSI Circuits/Technical Digest of Technical Papers, pp. 187-188 (2010).
In a read operation of a memory cell array, an output stage of the above DRAM core operates so that read data is transmitted to a data bus as parallel data of a predetermined number of bits and the read data is converted from parallel to serial form by an I/O circuit, thereby being externally outputted through DQ terminals. In a write operation of the memory cell array, write data is transmitted from the DQ terminals to the memory cell array through a reverse path. In order to improve the throughput in the above conventional configuration of the DRAM core, it is effective to increase the number of bits of the data bus and to increase an operating frequency. However, this causes a problem that the consumption current in the data bus increases in proportion to the number of bits of the data bus and the operating frequency respectively, which reaches an extremely larger value. Further, when driving many data buses in a data bus region, driving timings thereof overlap so as to increase temporal variation of the consumption current, and therefore this likely becomes power supply noise that affects the operation of the I/O circuit. Further, it is not easy to reduce line impedance of the power supplies in the data bus region and an I/O region for the purpose of dealing with such problems, since wiring structure is restricted in the DRAM core of which integration has been advanced. In this manner, in order to achieve the high-speed operation of the DRAM core, it is particularly required to overcome the performance problems due to the power supplies in the data bus region and the I/O region.